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19-2330; Rev 0; 1/02
Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs
General Description
The MAX5234/MAX5235 precision, dual-output, 12-bit digital-to-analog converters (DACs) consume only 360A from a single 5V (MAX5235) or 325A from a single 3V (MAX5234) supply. These devices feature output buffers that swing Rail-to-Rail(R). The internal gain amplifiers maximize the dynamic range of the DAC output. The MAX5234/MAX5235 feature a 13.5MHz 3-wire serial interface compatible with SPITM, QSPITM, and MICROWIRETM. Each DAC input is organized as an input register followed by a DAC register. A 16-bit shift register loads data into the input registers. Input registers update the DAC registers independently or simultaneously. In addition, programmable control bits allow power-down with 1k or 200k internal loads. The MAX5234/MAX5235 are fully specified over the extended industrial temperature range (-40C to +85C) and are available in space-saving 10-pin MAX packages. o Guaranteed 1/2LSB INL (max) o Low Supply Current 325A (Normal Operation) 0.4A (Full Power-Down Mode) o Single-Supply Operation 3V (MAX5234) 5V (MAX5235) o Space-Saving 10-Pin MAX Package o Output Buffers Swing Rail-to-Rail o Power-On Reset Clears Registers and DACs to Zero o Programmable Shutdown Modes with 1k or 200k Internal Loads o Resets to Zero o 13.5MHz SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial Interface o Buffered Output Drives 5k || 100pF
Features
MAX5234/MAX5235
Applications
Industrial Process Controls Automatic Test Equipment Digital Offset and Gain Adjustment Motion Control P-Controlled Systems
Ordering Information
PART MAX5234AEUB MAX5234BEUB MAX5235AEUB MAX5235BEUB TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 10 MAX 10 MAX 10 MAX 10 MAX INL (LSB) 0.5 1 0.5 1
Pin Configuration
TOP VIEW
OUTA 1 REFA GND LDAC 2 3 4 5 10 OUTB 9 REFB VDD DIN SCLK
MAX5234 MAX5235
8 7 6
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
CS
MAX
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V Digital Inputs to GND ..............................................-0.3V to +6V REF_, OUT_ to GND ................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.60mW/C above +70C) .........444mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5235
(VDD = +4.5V to +5.5V, GND = 0, VREFA = VREFB = +2.5V, RL= 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Full-Scale Voltage Full-Scale Temperature Coefficient Offset Temperature Coefficient Power-Supply Rejection DC Crosstalk REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Current in Shutdown Reference -3dB Bandwidth, Slew-Rate Limited Reference Feedthrough Signal-to-Noise plus Distortion Ratio SINAD VREF RREF IREF Input code = FFF hex, VREF_ = 0.5VP-P + 1.5VDC Input code = 000 hex, VREF_ = 3.6VP-P + 1.8VDC, f = 1kHz Input code = FFF hex, VREF_ = 2VP-P + 1.5VDC, f = 10kHz (Note 5) Minimum with code 555 hex and AAA hex 0.25 28 37 1 2.60 V k A VFS TCVFS TCVOS PSR 4.5V VDD 5.5V (Note 4) Code = FFF hex, TA = +25C (Note 3) Normalized to 4.095V 4.087 4.095 2 8 15 200 100 N INL DNL VOS (Note 2) MAX5235A (Note 1) MAX5235B (Note 1) 12 0.5 1 1 5 3 4.103 Bits LSB LSB mV LSB V ppm/C V/C V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING MODE PERFORMANCE 350 -80 79 kHz dB dB
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs
ELECTRICAL CHARACTERISTICS--MAX5235 (continued)
(VDD = +4.5V to +5.5V, GND = 0, VREFA = VREFB = +2.5V, RL= 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DIGITAL INPUT Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Output-Voltage Swing Time Required for Output to Settle After Turning on VDD Time Required for Output to Settle After Exiting Full PowerDown Time Required for Output to Settle After Exiting DAC PowerDown Digital Feedthrough Major-Carry Glitch Energy POWER SUPPLIES Power-Supply Voltage Power-Supply Current Power-Supply Current in PowerDown and Shutdown Modes VDD IDD ISHDN (Note 8) Full power-down mode One DAC shutdown mode Both DACs shutdown mode 4.5 360 1 190 26 5.5 450 5 215 42 V A A SR To 0.5LSB, VSTEP = 4V, 0.25V < VOUT < (VDD - 0.25V) (Note 6) (Note 7) 0.6 10 0 to VDD 70 V/s s V s VIH VIL VHYS Digital inputs = 0 or VDD 8 200 1 0.7 x VDD 0.3 x VDD V V mV A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5234/MAX5235
(Note 7)
70
s
(Note 7) CS = VDD, fSCLK = 100kHz, VSCLK = 5VP-P 5 40
60
s nV-s nV-s
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
ELECTRICAL CHARACTERISTICS--MAX5234
(VDD = +2.7V to +3.6V, GND = 0, VREFA = VREFB = +1.25V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Full-Scale Voltage Temperature Coefficient Offset Temperature Coefficient Power-Supply Rejection DC Crosstalk REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Current in Shutdown Reference -3dB Bandwidth, SlewRate Limited Reference Feedthrough Signal-to-Noise plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Output-Voltage Swing SR To 0.5LSB, VSTEP = 2V, 0.25V < VOUT < (VDD - 0.25V) (Note 6) 0.6 10 0 to VDD V/s s V VIH VIL VHYS Digital inputs = 0 or VDD 8 200 1 0.7 x VDD 0.3 x VDD V V mV A pF SINAD VREF RREF IREF Input code = FFF hex, VREF_ = 0.5VP-P + 0.75VDC Input code = 000 hex, VREF_ = 1.6VP-P + 0.8VDC, f = 1kHz Input code = FFF hex, VREF_ = 0.6VP-P + 0.9VDC, f = 10kHz (Note 5) Minimum with code 555 hex and AAA hex 0.25 28 37 1 1.50 V k A N INL DNL VOS GE VFS TCVFS TCVOS PSR 2.7V VDD 3.6V (Note 4) Code = FFF hex, TA = +25C (Note 3) Normalized to 2.0475V 2.041 2.0475 4 8 18 280 100 (Note 2) MAX5234A (Note 1) MAX5234B (Note 1) 12 0.5 1 1 5 6 2.054 Bits LSB LSB mV LSB V ppm/C V/C V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING MODE PERFORMANCE 350 -80 79 kHz dB dB
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs
ELECTRICAL CHARACTERISTICS--MAX5234 (continued)
(VDD = +2.7V to +3.6V, GND = 0, VREFA = VREFB = +1.25V, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Time Required for Output to Settle After Turning on VDD Time Required for Output to Settle After Exiting Full PowerDown Time Required for Output to Settle After Exiting DAC PowerDown Digital Feedthrough Major Carry Glitch Energy POWER SUPPLIES Power-Supply Voltage Power-Supply Current Power-Supply Current in PowerDown and Shutdown Modes VDD IDD ISHDN (Note 8) Full power-down mode One DAC shutdown mode Both DACs shutdown mode 2.7 325 0.4 175 25 3.6 430 5 200 40 A V A SYMBOL (Note 7) CONDITIONS MIN TYP MAX 60 UNITS s
MAX5234/MAX5235
(Note 7)
60
s
(Note 7) CS = VDD, fSCLK = 100kHz, VSCLK = 3VP-P 5 115
50
s nV-s nV-s
TIMING CHARACTERISTICS--MAX5235 (FIGURES 1 AND 2)
(VDD = +4.5V to +5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High LDAC Pulse Width Low CS Rise to LDAC Rise Hold Time SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tCS0 tCS1 tCSW tLDL tCSLD (Note 9) CONDITIONS MIN 74 30 30 30 0 30 0 10 30 75 30 40 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
TIMING CHARACTERISTICS--MAX5234 (FIGURES 1 AND 2)
(VDD = +2.7V to +3.6V, GND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High LDAC Pulse Width Low CS Rise to LDAC Rise Hold Time SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tCS0 tCS1 tCSW tLDL tCSLD (Note 9) CONDITIONS MIN 74 30 30 30 0 30 0 10 30 75 30 75 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Accuracy is guaranteed in the following way:
VDD 3 5 VREF_ 1.250 2.500 ACCURACY GUARANTEED FROM CODE 20 10 TO CODE 4095 4095
Note 2: Offset is measured at the code closest to 10mV. Note 3: Gain from VREF_ to VOUT_ is typically 1.638 x CODE/4096. Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change DAC B to full scale and measure VOUT for DAC A. Repeat the same measurement with DAC A and DAC B interchanged. DC crosstalk is the maximum VOUT measured. Note 5: The DAC output voltage is derived by gaining up VREF by 1.638 x CODE/4096. This gain factor may cause VOUT to try to exceed the supplies. The maximum value of VREF in the reference input range spec prevents this from happening at full scale. The minimum VREF value of 0.25V is determined by linearity constraints, not DAC functionality. Note 6: Accuracy is better than 1LSB for VOUT = 10mV to VDD - 180mV. Note 7: Guaranteed by design. Not production tested. Note 8: RLOAD = and digital inputs are at either VDD or GND. VOUT = full-scale output voltage. Note 9: This timing requirement applies only to CS rising edges, which execute commands modifying the DAC input register contents.
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs
Typical Operating Characteristics
(VDD = +5V (MAX5235) VDD = +3V (MAX5234), RL = 5k, CL = 100pF, VREF = +1.25V (MAX5234), VREF = +2.5V (MAX5235), CREF = 0.1F ceramic || 2.2F electrolytic, both DACs on, VOUT = full scale, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5234)
MAX5234 toc01
MAX5234/MAX5235
INTEGRAL NONLINEARITY vs. DIGITAL CODE (MAX5235)
MAX5234 toc02
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5234)
0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4
MAX5234 toc03
0.5 0.4 0.3 0.2 INL (LSB)
0.25 0.20 0.15 0.10 INL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25
0.4
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE
MAX5234 toc04
MAX5234 toc05
0.20 0.15 0.10 DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 0
350 SUPPLY CURRENT (A) 300 250 200 150 100 50 NO LOAD
350 SUPPLY CURRENT (A) 300 250 200 150 100 50 NO LOAD 0
500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE
0 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
MAX5234 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5234 toc07
MAX5235 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5234 toc08
MAX5234 FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE
0.45 0.40 SUPPLY CURRENT (A) 0.35 0.30 0.25 0.20 0.15 0.10
MAX5234 toc09
400 350 SUPPLY CURRENT (A) 300 250 200 150 100 50 NO LOAD 0 2.7 2.8 2.9 3.0 3.1 3.2
400 350 SUPPLY CURRENT (A) 300 250 200 150 100 50 NO LOAD 0
0.50
0.05 0 -40
NO LOAD -15 10 35 60 85
3.3
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
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MAX5234 toc06
0.25
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5235)
400
MAX5234 SUPPLY CURRENT vs. TEMPERATURE
400
MAX5235 SUPPLY CURRENT vs. TEMPERATURE
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5235) VDD = +3V (MAX5234), RL = 5k, CL = 100pF, VREF = +1.25V (MAX5234), VREF = +2.5V (MAX5235), CREF = 0.1F ceramic || 2.2F electrolytic, both DACs on, VOUT = full scale, TA = +25C, unless otherwise noted.)
MAX5234 BOTH DACs SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5234 toc10
MAX5234 ONE DAC SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5234 toc11
MAX5235 FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE
0.9 0.8 SUPPLY CURRENT (A) 0.7 0.6 0.5 0.4 0.3 0.2
MAX5234 toc12
30 29 28 SUPPLY CURRENT (A) 27 26 25 24 23 22 21 20 -40 NO LOAD -15 10 35 60
180 179 178 SUPPLY CURRENT (A) 177 176 175 174 173 172 171 170 NO LOAD -40 -15 10 35 TEMPERATURE (C) 60
1.0
0.1 0 85 -40
NO LOAD -15 10 35 TEMPERATURE (C) 60 85
85
TEMPERATURE (C)
MAX5235 BOTH DACs SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5234 toc13
MAX5235 ONE DAC SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5234 toc14
MAX5234 FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5234 toc15
30 29 28 SUPPLY CURRENT (A) 27 26 25 24 23 22 21 20 -40 NO LOAD -15 10 35 TEMPERATURE (C) 60
190 180 170 SUPPLY CURRENT (A) 160
2.0455 2.0454 2.0453 VOUT (V) 2.0452 2.0451 2.0450
150 140 130 120 110 100 90 NO LOAD -40 -15 10 35 TEMPERATURE (C) 60 85
NO LOAD 2.0449 -40 -15 10 35 TEMPERATURE (C) 60 85
85
MAX5235 FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5234 toc16
MAX5234 FULL-SCALE ERROR vs. RESISTIVE LOAD
MAX5234 toc17
MAX5235 FULL-SCALE ERROR vs. RESISTIVE LOAD
3.5 FULL-SCALE ERROR (LSB) 3.0 2.5 2.0 1.5 1.0 0.5 0
MAX5234 toc18
4.0970 4.0965 4.0960 VOUT (V) 4.0955 4.0950 4.0945 4.0940 4.0935 NO LOAD 4.0930 -40 -15 10 35 TEMPERATURE (C) 60
2.00 1.75 FULL-SCALE ERROR (LSB) 1.50 1.25 1.00 0.75 0.50 0.25 0
4.0
85
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 RL (k)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 RL (k)
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5235) VDD = +3V (MAX5234), RL = 5k, CL = 100pF, VREF = +1.25V (MAX5234), VREF = +2.5V (MAX5235), CREF = 0.1F ceramic || 2.2F electrolytic, both DACs on, VOUT = full scale, TA = +25C, unless otherwise noted.)
MAX5234 DYNAMIC RESPONSE RISE TIME
MAX5234 toc19
MAX5234/MAX5235
MAX5235 DYNAMIC RESPONSE RISE TIME
MAX5234 toc20
MAX5234 DYNAMIC RESPONSE FALL TIME
MAX5234 toc21
CS 1V/div CS 1V/div CS 2V/div
OUT_ 1V/div OUT_ 1V/div OUT_ 2V/div
2s/div
4s/div
2s/div
MAX5235 DYNAMIC RESPONSE FALL TIME
MAX5234 toc22
MAX5234 CROSSTALK
MAX5234 toc23
MAX5235 CROSSTALK
MAX5234 toc24
CS 2V/div
OUTB 2V/div
OUTB 5V/div
OUTA 1mV/div SHUTDOWN OUT_ 2V/div
OUTA 1mV/div SHUTDOWN
2s/div
2ms/div
40s/div
MAX5234 DIGITAL FEEDTHROUGH
MAX5234 toc25
MAX5235 DIGITAL FEEDTHROUGH
MAX5234 toc26
MAX5234 MAJOR-CARRY GLITCH
MAX5234 toc27
SCLK 2V/div
SCLK 5V/div
CS 1V/div
OUT_ 1mV/div
OUT_ 1mV/div
OUT_ 50mV/div AC -COUPLED
40s/div
40s/div
1s/div
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5235) VDD = +3V (MAX5234), RL = 5k, CL = 100pF, VREF = +1.25V (MAX5234), VREF = +2.5V (MAX5235), CREF = 0.1F ceramic || 2.2F electrolytic, both DACs on, VOUT = full scale, TA = +25C, unless otherwise noted.)
MAX5234 FULL-SCALE OUTPUT VOLTAGE vs. REFERENCE VOLTAGE
MAX5234 toc29
MAX5235 MAJOR-CARRY GLITCH
MAX5234 toc28
MAX5235 FULL-SCALE OUTPUT VOLTAGE vs. REFERENCE VOLTAGE
4.0 3.5 3.0 VOUT (V) 2.5 2.0 1.5 1.0 0.5 0
MAX5234 toc30
2.25 2.00 1.75 CS 2V/div 1.50 VOUT (V) 1.25 1.00 0.75 OUT_ 50mV/div AC-COUPLED 2s/div 0.50 0.25 0 0 0.25 0.50 0.75 1.00
4.5
1.25
0
0.5
1.0
1.5
2.0
2.5
VREF (V)
VREF (V)
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME OUTA REFA GND LDAC CS SCLK DIN VDD REFB OUTB FUNCTION DAC A Output Reference for DAC A Ground Load DACs A and B Chip Select Input Shift Register Serial Clock Input Serial Data Input Positive Supply Reference for DAC B DAC B Output
output voltage proportional to the digital input code with an inverted rail-to-rail ladder network (Figure 3).
External Reference
The reference inputs accept both AC and DC values with a voltage range extending from 0.25V to 2.6V for the MAX5235 and 0.25V to 1.5V for the MAX5234. For proper operation do not exceed the input voltage range limits. Determine the output voltage using the following equation: VOUT_ = (VREF_ x NB / 4096) x 1.6384V/V where NB is the numeric value of the DACs binary input code (0 to 4095), VREF_ is the reference voltage, and 1.6384V/V is the gain of the internal output amplifier. The code-dependent reference input impedance ranges from a minimum of 28k to several G at code 0. The code-dependent reference input capacitance is typically 23pF.
Detailed Description
The MAX5234/MAX5235 12-bit, voltage-output DACs are easily configured with a 3-wire SPI, QSPI, MICROWIRE serial interface. The devices include a 16bit data-in/data-out shift register and have an input consisting of an input register and a DAC register. In addition, these devices employ precision trimmed internal resistors to produce a gain of 1.6384V/V, maximizing the output voltage swing, and a programmable shutdown output impedance of 1k or 200k. The full-scale output voltage is 4.095V for the MAX5235 and 2.0475V for the MAX5234. These devices produce a weighted
10
Output Amplifier
The output amplifiers have internal resistors that provide for a gain of 1.6384V/V. These trimmed resistors minimize gain error. The output amplifiers have a typical slew rate of 0.6V/s and settle to 1/2LSB within 10s (typ) with a load of 5k in parallel with 100pF. Use the serial interface to set the shutdown output impedance of the amplifiers to 1k or 200k.
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
CS COMMAND EXECUTED
SCLK 1 DIN C2 C1 C0 D11 D10 D9 D8 8 D7 D6 9 D5 D4 D3 D2 D1 D0 16 S0 (1)
Figure 1. Serial Interface Timing
tLDL tCSLD LDAC tCSW CS tCSO SCLK tCH tCP DIN tDS tDH tCL tCSS tCSH tCS1
Figure 2. Detailed Serial Interface Timing
Serial Interface
The 3-wire serial interface (SPI, QSPI, and MICROWIRE compatible) used in the MAX5234/MAX5235 allows for complete control of DAC operations (Figures 4 and 5). Figures 1 and 2 show the timing for the serial interface. The serial word consists of 3 control bits followed by 12 data bits (MSB first) and 1 sub-bit as described in Tables 1, 2, and 3. When the 3 control bits are all zero or all 1, D11-D8 are used as additional control bits, allowing for greater DAC functionality. The digital inputs allow any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC register(s) simultane-
ously. The control bits and D11-D8 allow the DACs to operate independently. Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI and MICROWIRE), with CS low during this period. The control bits and D11-D8 determine which registers update and the state of the registers when exiting shutdown. The 3-bit control and D11-D8 determine the following: * Registers to be updated * Selection of the power-down modes The general timing diagram of Figure 1 illustrates data acquisition. Driving CS low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the
11
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
Table 1. Serial Data Format
MSB
<----------- 16 bits of serial data -----------> LSB
MSB......12 Data Bits.....LSB D11................................D0 Sub Bit S0
3 Control Bits C2...C0
either DAC input register, then LDAC must remain asserted for at least 30ns following the CS rising edge. This requirement applies only for serial commands that modify the value of the DAC input registers.
Applications Information
Definitions
Integral Nonlinearity (INL) Integral nonlinearity (Figure 6a) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every single step. Differential Nonlinearity (DNL) Differential nonlinearity (Figure 6b) is the difference between an actual step height and the ideal value of 1LSB. If the magnitude of the DNL is less than 1LSB, the DAC guarantees no missing codes and is monotonic. Offset Error The offset error (Figure 6c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated for by trimming. Gain Error Gain error (Figure 6d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value within the converter's specified accuracy. Digital Feedthrough Digital feedthrough is noise generated on the DAC's output when any digital input transitions. Proper board layout and grounding significantly reduces this noise, but there is always some feedthrough caused by the DAC itself.
register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers, depending on the control bits and D11-D8. The maximum clock frequency guaranteed for proper operation is 13.5MHz. Figure 2 depicts a more detailed timing diagram of the serial interface.
Power-Down and Shutdown Modes
As described in Tables 2 and 3, several serial interface commands put one or both of the DACs into shutdown mode. Shutdown modes are completely independent for each DAC. In shutdown, the amplifier output becomes high impedance, and OUT_ terminates to GND through the 200k (typ) gain resistors. Optionally (see Tables 2 and 3), OUT_ can have a termination of 1k to GND. Full power-down mode shuts down the main bias generator and both DACs. The shutdown impedance of the DAC outputs can still be controlled independently, as described in Tables 2 and 3. A serial interface command exits shutdown mode and updates a DAC register. Each DAC can exit shutdown at the same time or independently (see Tables 2 and 3). For example, if both DACs are shut down, updating the DAC A register causes DAC A to power up, while DAC B remains shut down. In full power-down mode, powering up either DAC also powers up the main bias generator. To change from full power-down to both DACs shutdown mode requires the waking of at least one DAC between states. When powering up the MAX5234/MAX5235 (powering VDD), allow 60s (MAX5234) or 70s (MAX5235) for the output to stabilize. When exiting full power-down mode, allow 60s max (MAX5234) or 70s max (MAX5235) for the output to stabilize. When exiting DAC shutdown mode, allow 50s max (MAX5234) or 60s max (MAX5235) for the output to stablize.
Load DAC Input (LDAC)
Asserting LDAC asynchronously loads the DAC registers from their corresponding input registers (DACs that are shut down remain shut down). The LDAC input is totally asynchronous and does not require any activity on CS, SCLK, or DIN in order to take effect. If LDAC is asserted coincident with a rising edge of CS, which executes a serial command modifying the value of
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Unipolar Output
Figure 7 shows the MAX5234/MAX5235 configured for unipolar, rail-to-rail operation with a gain of 1.6384V/V. The MAX5235 produces a 0 to 4.095V output with 2.5V reference while the MAX5234 produces a range of 0 to
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
Table 2. Serial Interface Programming Commands
16-BIT SERIAL WORD C2 0 0 0 C1 0 1 1 C0 1 0 1 D11..............D0 12-bit DAC data 12-bit DAC data 12-bit DAC data S0* 0 0 0 FUNCTION Load input register A; DAC registers are unchanged. Load input register A; all DAC registers are updated. Load all DAC registers from the shift register (start up both DACs with new data, and load the input registers). Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). Load input register B; DAC registers are unchanged. Load input register B; all DAC registers are updated. Power down both DACs respectively according to bits P1A and P1B (see Table 3). Internal bias remains active. Update DAC register A from input register A (start up DAC A with data previously stored in input register A). Full power-down. Power down the main bias generator and power down both DACs respectively according to bits P1A and P1B (see Table 3). Update DAC register B from input register B (start up DAC B with data previously stored in input register B). Power down DAC A according to bit P1A (see Table 3). Power down DAC B according to bit P1B (see Table 3).
1 1 1 1 0
0 0 1 1 0
0 1 0 1 0
XXXXXXXXXXXX 12-bit DAC data 12-bit DAC data P1A P1B X X X X X X X X X X 001XXXXXXXXX
0 0 0 0 0
0
0
0
0 1 1 P1A P1B X X X X X X X
0
0 0 0
0 0 0
0 0 0
101XXXXXXXXX 1 1 0 P1A X X X X X X X X 1 1 1 P1B X X X X X X X X
0 0 0
X = Don't care. * = S0 must be zero for proper operation.
2.0475V output with a 1.25V reference. Table 4 lists the unipolar output codes.
Table 3. P1 Shutdown Modes
P1(A/B) 0 1 SHUTDOWN MODE Shut down with internal 1k load to GND Shut down with internal 200k load to GND
Bipolar Output
The MAX5234/MAX5235 can be configured for a bipolar output, as shown in Figure 8. The output voltage is given by the equation: VOUT = VREF [((1.6348 x NB) / 4096) - 1] where NB represents the numeric value of the DAC's binary input code. Table 5 shows digital codes and the corresponding output voltage for Figure 8's circuit.
Digital Calibration and Threshold Selection
Figure 10 shows the MAX5234/MAX5235 in a digital calibration application. With a bright light value applied to the photodiode (on), the DAC is digitally ramped until it trips the comparator. The microprocessor (P) stores this "high" calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The P then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis.
Using an AC Reference
In applications where the reference has an AC signal component, the MAX5234/MAX5235 have multiplying capabilities within the reference input voltage range specifications. Figure 9 shows a technique for applying a sinusoidal input to REF_, where the AC signal is offset before being applied to the reference input.
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
Table 4. Unipolar Code Table (Gain = 1.6384)
DAC CONTENTS MSB LSB ANALOG OUTPUT
77.25k 121k
1111 1111 1 111 (0)
4095 + VREF x 1.6384 4096 2049 + VREF x 1.6384 4096 2048 + VREF x 1.6384 = VREF 4096 2047 + VREF x 1.6384 4096 1 + VREF x 1.6384 4096
0V
REF_ GND 2R 2R D0
R
R
R
OUT_
2R D9
2R D10
2R D11 1k
1000 0000 0 001 (0)
1000 0000 0 000 (0)
SHOWN FOR ALL ONES ON DAC
0111 1111 1 111 (0)
Figure 3. Simplified DAC Circuit Diagram
5V
0000 0000 0001 (0) 0000 0000 0 000 (0)
Note: () are for the sub-bit.
SS DIN MOSI
Table 5. Bipolar Code Table
DAC CONTENTS MSB LSB ANALOG OUTPUT
MAX5234 MAX5235
SCLK
SCK
SPI/QSPI PORT
1111 1111 1 111 (0)
2047 + VREF 2048 1 + VREF 2048
0V
CS
I/O
Figure 4. SPI/QSPI Interface Connections
1000 0000 0 001 (0) 1000 0000 0 000 (0) 0111 1111 111 (0)
1 -VREF 2048 2047 -VREF 2048 2048 -VREF = - VREF 2048
MAX5234 MAX5235
SCLK
SK
DIN
SO
MICROWIRE PORT
0000 0000 001 (0)
CS
I/O
0000 0000 000 (0)
Figure 5. Connections for MICROWIRE
Note: () are for the sub-bit. 14 ______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
7 6 ANALOG OUTPUT VALUE (LSB) ANALOG OUTPUT VALUE (LSB) 6 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (1/4LSB ) AT STEP 011 (1/2LSB ) 5 4 3 1LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+1/4LSB) 1LSB DIFFERENTIAL LINEARITY ERROR (-1/4LSB)
Figure 6a. Integral Nonlinearity
Figure 6b. Differential Nonlinearity
3 ANALOG OUTPUT VALUE (LSB)
ACTUAL DIAGRAM ANALOG OUTPUT VALUE (LSB)
7
IDEAL FULL-SCALE OUTPUT GAIN ERROR (-1 1/4LSB)
2 IDEAL DIAGRAM 1
6 IDEAL DIAGRAM 5 ACTUAL FULL-SCALE OUTPUT
0
ACTUAL OFFSET OFFSET ERROR POINT (+1 1/4LSB) IDEAL OFFSET POINT 000 001 010 011 DIGITAL INPUT CODE
4 0 000 100 101 110 111 DIGITAL INPUT CODE
Figure 6c. Offset Error
Figure 6d. Gain Error
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
REF_ 5V/3V VDD REF_ 5V/3V VDD
10k
10k
MAX5234 MAX5235
121k
MAX5234 MAX5235
77.25k OUT_
121k V+
77.25k
DAC_ DAC_
0.06384R OUT_ R V-
VOUT
1k
GND GAIN = 1.6384V/V
1k
GND
Figure 7. Unipolar Output Circuit (Rail-to-Rail)
Figure 8. Bipolar Output Circuit
5V/3V
26k AC REFERENCE INPUT
5V/3V
V+
REF_ 5V/3V VDD
MAX495
PHOTODIODE
500mVP-P
10k
REF_
VDD
MAX5234 MAX5235
121k
121k V+ 77.25k
77.25k
DAC_
OUT_
OUT_
VOUT
P DIN
DAC_
V-
MAX5234 MAX5235
1k
1k
RPULLDOWN
GND
GND
Figure 9. External Reference with AC Components
Figure 10. Digital Calibration
Digital Control of Gain and Offset
The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as transducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 11).
Sharing a Common DIN Line
Several MAX5234/MAX5235 may share one common DIN signal line (Figure 12). In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. The SCLK and DIN lines are shared by all devices, but each IC needs its own dedicated CS line.
Power-Supply Considerations
On power-up, the input and DAC registers clear (set to zero code). Bypass the power supply with a 4.7F
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
VDD
121k
VIN
REFA CS SCLK DIN REFB
MAX5234 MAX5235
77.25k OUTA INPUT REG A INPUT REG B DAC REG A DAC REG B DAC A
R1 R2
VOUT
SHIFT REGISTER
DAC B
OUTB 77.25k
R3 R4
VREF
121k
VOUT = (GAIN) (OFFSET) R2 = VIN 2NA 1 + R4 - VREF 2NB R4 4096 R1 + R2 R3 4096 R3 NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DAC A. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DAC B.
GND
Figure 11. Digital Control of Gain and Offset
DIN SCLK CS1 CS2 CS3
TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5234 MAX5235
SCLK DIN SCLK DIN
MAX5234 MAX5235
SCLK DIN
MAX5234 MAX5235
Figure 12. Multiple MAX5234/MAX5235 Sharing a Common DIN Line
capacitor in parallel with a 0.1F capacitor to GND. Minimize lead lengths to reduce lead inductance.
Grounding and Layout Considerations
Digital and AC transient signals on GND can create noise at the output. Connect GND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane or star connect all ground return paths
back to the MAX5234/MAX5235 GND. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required.
Chip Information
TRANSISTOR COUNT: 4184 PROCESS: BiCMOS
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs MAX5234/MAX5235
Functional Diagram
GND
VDD
REFA
121k LDAC DECODE CONTROL 77.25k OUTA 16-BIT SHIFT REGISTER INPUT REG A DAC REG A DAC A 1k
SR CONTROL
MAX5234 MAX5235
121k
77.25k OUTB INPUT REG B DAC REG B DAC B 1k
CS
DIN
SCLK
REFB
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Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs
Package Information
10LUMAX.EPS
MAX5234/MAX5235
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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